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All Papers Journal Articles Conference Papers Workshop and Poster Theses

All Technical Papers (by date)
Conventional Processor Architecture and Compilers, Performance Modeling
Secure, Dependable and Autonomic Computing, DRM
Embedded Computing
Low-Power Techniques
FPGA Techniques
3D ICs, SoC, Physical Design and EDA Tools
Multicore, Parallel Architecture and Systems
Support for 3D Graphics



All Refereed Papers

ACM TACODong Hyuk Woo, Joshua B. Fryman, Allan D. Knies, and Hsien-Hsin S. Lee. "Chameleon: Virtualizing Idle Acceleration Cores of A Heterogeneous Multi-Core Processor for Caching and Prefetching." Accepted by ACM Transactions on Architecture and Code Optimization.
IEEE MICRODong Hyuk Woo, Joshua B. Fryman, Allan D. Knies, Marsha Eng, and Hsien-Hsin S. Lee. "POD: A 3D-Integrated Broad-Purpose Acceleration Layer." In IEEE MICRO special issue on Accelerator Architectures, Vol. 28, No. 4, pp.28-40, July/August, 2008.
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GH-08Ahmad Sharif and Hsien-Hsin S. Lee. "Total Recall: A Debugging Framework for GPUs." In Proceedings of the ACM SIGGRAPH/Eurographics Workshop of Graphics Hardware, pp.13-20, Sarajevo, Bosnia-Herzegovina, June, 2008.
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GH-06Weidong Shi, Hsien-Hsin S. Lee, Richard M. Yoo, and Alexandra Boldyreva. "A Digital Rights Enabled Graphics Processing System." In Proceedings of the ACM SIGGRAPH/Eurographics Workshop of Graphics Hardware, pp.17-26, Vienna, Austria, September, 2006.
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JILPHsien-Hsin S. Lee, Gary S. Tyson, and Matthew K. Farrens. "Improving Bandwidth Utilization using Eager Writebacks." In Journal of Instruction-Level Parallelism, Vol. 3, 2001.
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MICRO-33Hsien-Hsin S. Lee, Gary S. Tyson, and Matthew K. Farrens. "Eager Writeback - a Technique for Improving Bandwidth Utilization." In Proceedings of the 33rd ACM/IEEE International Symposium on Microarchitecture, pp.11-21, Monterey, California, December, 2000. (Best Paper Awarded)
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ITJPaul Zagacki, Deep Buch, Emile Hsieh, Daniel Melaku, Vladimir Pentkovski, and Hsien-Hsin Lee. "Architecture of a 3D Software Stack for Peak Pentium III Processor Performance." In Intel Technology Journal, Q2, May, 1999.
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