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All Papers Journal Articles Conference Papers Workshop and Poster Book Chapters Theses

All Technical Papers (by date)
Conventional Processor Architecture and Compilers, Performance Modeling
Secure, Dependable and Autonomic Computing, DRM
Embedded Computing
Low-Power Techniques
FPGA Techniques
3D ICs, SoC, Physical Design and EDA Tools
Multicore, Parallel Architecture and Systems
Support for 3D Graphics



All Refereed Papers

IEEE TVLSIDong Hyuk Woo, Nak Hee Seong, and Hsien-Hsin S. Lee. "Pragmatic Integration of An SRAM Row Cache in Heterogeneous 3-D DRAM Architecture using TSV." In IEEE Transactions on Very Large Scale Integration Systems, Vol.21, No.1, pp.1-13, January, 2013.
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ICCSAHong Jun Choi, Young Jin Park, Hsien-Hsin Lee, and Cheol Hong Kim. "Adaptive Dynamic Frequency Scaling for Thermal-Aware 3D Multi-core Processors." In the Proceedings of the 12th International Conference on Computational Science and Its Applications, pp.602-612, Salvador de Bahia, Brazil, 2012.
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ISSCCDae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, and Sung Kyu Lim. "3D-MAPS: 3D Massively Parallel Processor with Stacked Memory." In Technical Digest of the IEEE International Solid-State Circuits Conference, pp.188-190, San Francisco, CA, 2012.
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3DICXiaodong Wang, Dilip Vasudevan, and Hsien-Hsin S. Lee. "Global Built-In Self-Repair for 3-D Memories with Redundancy Sharing and Parallel Testing." In Proceedings of the IEEE International 3D System Integration Conference, Osaka, Japan, 2012.
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ICCDDean L. Lewis, Shreepad Panth, Xin Zhao, Sung Kyu Lim, and Hsien-Hsin S. Lee. "Designing 3D Test Wrappers for Pre-bond and Post-bond Test of 3D Embedded Cores." In Proceedings of the XXIX IEEE International Conference on Computer Design, pp.90-95, University of Massachusetts, Amherst, USA, October, 2011.
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MWSCASDong Hyuk Woo, Nak Hee Seong, and Hsien-Hsin S. Lee. "Heterogeneous Die Stacking of SRAM Row Cache and 3-D DRAM: An Empirical Design Evaluation." In Proceedings of the 54th IEEE International Midwest Symposium on Circuits and Systems, pp.1-4, Seoul, Korea, August, 2011. (An Invited Paper)
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ACM TODAESMichael B. Healy, Fayez Mohamood, Hsien-Hsin S. Lee, and Sung Kyu Lim. "Integrated Microarchitectural Floorplanning and Runtime Controller for Inductive Noise Mitigation." ACM Transactions on Design Automation of Electronic Systems, Vol.16, Issue 4, October, 2011.
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IEEE TCADXin Zhao, Dean Lewis, Hsien-Hsin S. Lee, and Sung Kyu Lim. "Low-Power Clock Tree Design for Pre-Bond Testing of 3D Stacked ICs." In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, Issue 5, pp.732-745, 2011.
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3D-TESTDean Lewis, Michael Healy, Mohammad Hossain, Tzu-Wei Lin, Mohit Pathak, Hemant Sane, Sung Kyu Lim, Gabriel Loh, and Hsien-Hsin S. Lee. "Design and test of 3D-MAPS, a 3D Die-Stack Many-Core Processor." In the first IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (poster), Austin, Texas, November, 2010.
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CICCMichael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, and Sung Kyu Lim. "Design and Analysis of 3D-MAPS: A Many-Core 3D Processor with Stacked Memory." In Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, California, September, 2010. (Intel/CICC Student Scholarship Award)
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ACM TACODong Hyuk Woo, Joshua B. Fryman, Allan D. Knies, and Hsien-Hsin S. Lee. "Chameleon: Virtualizing Idle Acceleration Cores of A Heterogeneous Multi-Core Processor for Caching and Prefetching." In ACM Transactions on Architecture and Code Optimization, Vol. 7, No. 1, pp.3:1-3:35, April, 2010.
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ASPLOS XVDong Hyuk Woo and Hsien-Hsin S. Lee. "COMPASS: A Programmable Data Prefetcher Using Idle GPU Shaders." In Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, pp.297-309, Pittsburgh, PA, March, 2010.
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HPCA-16Dong Hyuk Woo, Nak Hee Seong, Dean L. Lewis, and Hsien-Hsin S. Lee. "An Optimized 3D-Stacked Memory Architecture by Exploiting Excessive, High-Density TSV Bandwidth." In Proceedings of the 16th International Symposium on High-Performance Computer Architecture, pp.429-440, Bangalore, India, January, 2010.
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ICCADXin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, and Sung Kyu Lim. "Pre-bond Testable Low-Power Clock Tree Design for 3D Stacked ICs." In Proceedings of the 2009 International Conference on Computer-Aided Design, pp.184-190, San Jose, CA, November, 2009. (Nominated for the Best Paper Award by ICCAD-09)
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3DICDean L. Lewis and Hsien-Hsin S. Lee. "Architectural Evaluation of 3D Stacked RRAM Caches." In IEEE International 3D System Integration Conference, San Francisco, CA, September, 2009.
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IEEE D&THsien-Hsin S. Lee and Krishnendu Chakrabarty. "Test Challenges for 3D Integrated Circuits." In IEEE Design & Test of Computers, Special Issue on 3D IC Design and Test, Vol.26, Issue 5, pg. 26-35, Sept/Oct, 2009.
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ISVLSIDean L. Lewis and Hsien-Hsin S. Lee. "Testing Circuit-Partitioned 3D IC Designs." In IEEE Computer Society Annual Symposium on VLSI, Tampa, FL, May, 2009.
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ISVLSIDean L. Lewis, Sudhakar Yalamanchili, and Hsien-Hsin S. Lee. "High Performance Non-blocking Switch Design in 3D Die-Stacking Technology." In IEEE Computer Society Annual Symposium on VLSI, Tampa, FL, May, 2009.
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3D IntegrationDean L. Lewis and Hsien-Hsin S. Lee. "Test Strategies for 3D Die Stacked Integrated Circuits." In Workshop on 3D Integration --- Technology, Architecture, Design, Automation, and Test in conjunction with Design, Automation and Test in Europe (DATE-09), Nice, France, April, 2009.
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ASP-DACMichael Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, and Sung Kyu Lim. "Thermal Optimization in Multi-Granularity Multi-Core Floorplanning." In Proceedings of the 14th IEEE/ACM Asia South Pacific Design Automation Conference, pp.43-48, Yokohama, Japan, 2009.
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IEEE MICRODong Hyuk Woo, Joshua B. Fryman, Allan D. Knies, Marsha Eng, and Hsien-Hsin S. Lee. "POD: A 3D-Integrated Broad-Purpose Acceleration Layer." In IEEE MICRO special issue on Accelerator Architectures, Vol. 28, No. 4, pp.28-40, July/August, 2008.
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SAMOS VIIIChinnakrishnan S. Ballapuram and Hsien-Hsin S. Lee. "Improving TLB Energy for Java Applications on JVM." In Proceedings of the IEEE International Symposium on Systems, Architectures, Modeling and Simulation, pp.218-223, Samos, Greece, July, 2008.
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ASP-DACMichael Healy, Fayez Mohamood, Hsien-Hsin S. Lee, and Sung Kyu Lim. "A Unified Methodology for Power Supply Noise Reduction in Modern Microarchitecture Design." In Proceedings of the 13th IEEE/ACM Asia South Pacific Design Automation Conference, pp.611-616, Seoul, Korea, January, 2008.
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MICRO-40Mrinmoy Ghosh and Hsien-Hsin S. Lee. "Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs." In Proceedings of the 40th ACM/IEEE International Symposium on Microarchitecture, pp.134-145, Chicago, IL, December, 2007.
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ITC-07Dean L. Lewis and Hsien-Hsin S. Lee. "A Scan-Island Based Design Enabling Pre-bond Testability in Die-Stacked Microprocessors." In Proceedings of the International Test Conference, Santa Clara, CA, October, 2007.
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ASP-DACFayez Mohamood, Michael Healy, Sung Kyu Lim, and Hsien-Hsin S. Lee. "Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling." In Proceedings of the 12th Asia and South Pacific Design Automation Conference, pp.786-791, Yokohama, Japan, January, 2007.
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IEEE TCADMichael Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, and Gabriel H. Loh. "Multi-Objective Microarchitectural Floorplanning For 2D and 3D ICs." In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 1, pp.38-52, 2007.
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MICRO-39Fayez Mohamood, Michael Healy, Sung Kyu Lim, and Hsien-Hsin S. Lee. "A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design." In Proceedings of the ACM/IEEE International Symposium on Microarchitecture, pp.3-14, Orlando, Florida, December, 2006.
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IBM PAC2Mrinmoy Ghosh and Hsien-Hsin S. Lee. "DRAMdecay: Using Decay Counters to Reduce Energy Consumption in DRAMs." In Proceedings of the 3rd Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=AC2), Yorktown Heights, NY, October, 2006.
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CASES-06Dong Hyuk Woo, Mrinmoy Ghosh, Emre Özer, Stuart Biles, and Hsien-Hsin S. Lee. "Reducing Energy of Virtual Cache Synonym Lookup using Bloom Filters." In Proceedings of the ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp.179-189, Seoul, Korea, October, 2006.
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CASES-06Chinnakrishnan Ballapuram, Kiran Puttaswamy, Gabriel H. Loh, and Hsien-Hsin S. Lee. "Entropy-based Low Power Data TLB Design." In Proceedings of the ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp.304-311, Seoul, Korea, October, 2006.
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IEEE TCADMongkol Ekpanyapong, Jacob Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, and Sung Kyu Lim. "Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design." In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No.7, pp.1289-1300, July, 2006.
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ARCS-06Mrinmoy Ghosh, Emre Özer, Stuart Biles, and Hsien-Hsin S. Lee. "Efficient System-on-Chip Energy Management with a Segmented Bloom Filter." In Proceedings of the 19th International Conference on Architecture of Computing Systems, pp. 283-297,Frankfurt/Main, Germany, March, 2006.
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DATE-06Michael Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, and Gabriel H. Loh. "Microarchitectural Floorplanning Under Performance and Temperature Tradeoff." In Proceedings of the Design, Automation and Test in Europe, pp.1288-1293, Munich, Germany, March, 2006.
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DAC-42Taeweon Suh, Daehyun Kim, and Hsien-Hsin S. Lee. "Cache Coherence Support for Non-Shared Bus Architecture on Heterogeneous MP SoCs." In Proceedings of the 42nd Design Automation Conference (DAC-42), pp.553-558, Anaheim, California, June, 2005.
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ISCASMongkol Ekpanyapong, Sung Kyu Lim, Chinnakrishnan Ballapuram, and Hsien-Hsin S. Lee. "Wire-driven Microarchitectural Design Space Exploration." In the Proceedings of the 2005 IEEE International Symposium on Circuits and Systems, pp.1867-1870, Kobe, Japan, May, 2005.
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WARFPTaeweon Suh, Hsien-Hsin S. Lee, Sally A. McKee, and Martin Schulz. "Evaluating System-wide Monitoring Capsule Design Using Xilinx Virtex-II Pro FPGA." In Workshop on Architecture Research using FPGA Platforms in conjunction with International Symposium on High-Performance Computer Architecture, San Francisco, CA, February, 2005.
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WARFPChristopher R. Clark, Ripal Nathuji, and Hsien-Hsin S. Lee. "Using an FPGA as a Prototyping Platform for Multi-core Processor Applications." In Workshop on Architectural Research using FPGA Platforms in conjunction with International Symposium on High-Performance Computer Architecture, San Francisco, CA, February, 2005.
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IEEE MICROTaeweon Suh, Hsien-Hsin S. Lee, and Douglas M. Blough. "Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 2." In IEEE MICRO, pp.70-78, September/October, 2004.
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IEEE MICROTaeweon Suh, Hsien-Hsin S. Lee, and Douglas M. Blough. "Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1." In IEEE MICRO special issue on Embedded Systems: Architecture, Design and Tools, pp.33-41, July/August, 2004.
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DAC-41Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, and Sung Kyu Lim. "Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design." In Proceedings of the 41st Design Automation Conference, pp. 634-639, San Diego, California, June, 2004.
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DATETaeweon Suh, Douglas M. Blough, and Hsien-Hsin S. Lee. "Supporting Cache Coherence in Heterogeneous Multiprocessor Systems." In Proceedings of the Design, Automation and Test in Europe Conference, pp.1150-1155, Paris, France, February, 2004.
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ICCADYuvraj S. Dhillon, Abdulkadir U. Diril, Abhijit Chatterjee, and Hsien-Hsin S. Lee. "Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level." In Digest of Technical Papers of the International Conference on Computer-Aided Design, pp.693-700, San Jose, California, November, 2003.
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